Generally, a unit cell of a static random access memory (hereinafter abbreviated “SRAM”) includes six transistors (6-Tr). More specifically, a unit cell typically includes two drive transistors, two access transistors, and two load elements.
A circuit and layout of a prior art 6-Tr SRAM unit cell will now be explained. FIG. 1 is a circuit diagram of the prior art SRAM device unit cell. FIG. 2 is a layout of the prior art SRAM device unit cell.
Referring to FIG. 1 and FIG. 2, the SRAM device unit cell includes access transistors Q1 (250) and Q3 (260) having gates connected to a wordline WL and drains connected to positive and negative bitlines BL and/BL, respectively. The SRAM device unit cell also includes load elements Q5 (210) and Q6 (220) having their sources connected to a power voltage Vcc. The unit cell also includes a positive cell node N which is commonly connected to a drain of the load element Q5 (210) and to the source of the access transistors Q1 (250). The unit cell also has a negative cell node/N which is commonly connected to a drain of the load element Q6 (220) and to the source of the access transistors Q3 (260). The unit cell is further provided with drive transistors Q2 (230) and Q4 (240). The drive transistor Q2 is connected to the drain of the load element Q5. The drive transistor Q4 is connected to the drain of the load element Q6. The gates of the drive transistors Q2, Q4 are respectively connected to the gates of the load elements Q5, Q6 in a CMOS configuration. Further, the gates of the drive transistors Q2 (230), Q4 (240) are cross-linked to the positive and negative cell nodes N,/N, respectively.
The area enclosed by a dotted-line square in FIG. 2 corresponds to the unit cell of the 6-Tr SRAM device. Each area enclosed by a solid line within the unit cell corresponds to an active area. Moreover, each hatched square indicates a contact hole 206.
Referring to FIG. 2, a common gate electrode 271 is provided to apply a sync signal to the gates of the load element 210 and the drive transistor 230. Upper metal lines (not shown in the drawing) are formed on an insulating inter layer covering the six transistors. Contact holes are formed in the insulating interlayer to connect the six transistors to the upper metal lines. Each of the contact holes 206 is filled with a conductive plug. In the unit cell of the SRAM device shown in FIG. 2, eight and half (8.5) contact holes are formed for the connections between the transistors and the metal lines.
Specifically, the 8.5 contact holes include 6.5 contact holes for connections to the junctions (source/drain) of the transistors and 2 contact holes for connection to the common gate electrodes of the transistors.
As the design rule is reduced due to the greatly increasing degree of integration in a semiconductor device, the unit cell area or size of the SRAM device is reduced as well. However, the unit cell of the 6-Tr SRAM device requires the 8.5 contact holes which occupy a considerable fixed area within the unit cell.
To keep up with the rapidly increasing degree of integration of the SRAM device, the number of contact holes required for the unit cell of the SRAM device must be lowered as the design rule is reduced.
A prior art method of reducing the number of the contact holes in the unit cell of the SRAM device will now be explained with reference to FIG. 3. FIG. 3 is a cross-sectional view of the SRAM device unit cell in FIG. 2 taken along cutting line A-A′.
Referring to FIG. 3, a field oxide layer 202 is provided in a field area to define an active area of a semiconductor substrate 201. Gate electrodes 203, 204 of a drive transistor and a load element are formed in the active areas of the substrate 201. Sources S and drains D are provided to on opposite sides of the gate electrodes 203, 204.
A gate insulating layer (not shown in the drawing) is provided beneath each of the gate electrodes 203, 204. A spacer (not shown in the drawing) may be provided on each sidewall of the gate electrodes 203, 204.
A common gate electrode 271 is formed between the gate electrodes 203, 204 to apply a sync signal to the gate electrodes 203, 204 of the load element and the drive transistor.
An insulating layer 205 is formed on the substrate 201 including the common gate electrode 271. An upper line (not shown in the drawing) is formed on the insulating interlayer 205.
The source/drain S/D and the common gate electrode 271 are electrically connected to the upper line via respective plugs 207. The plugs 207 fill contact holes 206 provided in the insulating interlayer 205. The contact holes 206 are formed by selectively etching the insulating interlayer 205 to expose two junction layers (source or drain) of the two transistors and the common gate electrode 271.
In the unit cell of the illustrated prior art SDRAM device, three contact holes are required for electrical connections between the upper line and the load element, the common gate electrode 271 and the drive transistor.
As shown in FIG. 2, the contact holes provided for the load element, the common gate electrode 271, and the drive transistor are aligned on almost the same line. Since the contact holes are nearly aligned on the same straight line and are densely aggregated, the process margin is lowered due to the reduced design rule.
Moreover, as the number of contact holes required for the unit cell of the SRAM device is fixed at 8.5, it is difficult to increase the degree of integration of the semiconductor device.
Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.